1. Field of the Invention
The invention relates generally to semiconductor power devices. More particularly, this invention relates to new configurations and methods for manufacturing field stop insulated gate bipolar transistor (IGBT) to minimize the buffer and emitter charge variations.
2. Description of the Prior Art
Conventional technologies to configure and manufacture vertical power devices, particularly the field stop insulated gate bipolar transistor (IGBT), have difficulties and limitations due to the uncertainties in controlling the thickness and dopant concentration of the backside layers.
Field stop IGBTs include a (n-type) field stop (buffer) layer at the bottom of the drift region, and a thin implanted (p-type) collector region below the buffer layer. The collector region has a reduced number of charges compared to punch through IGBTs, and so has controlled minority carrier injection. The buffer layer terminates the electric field (i.e., acts as a “field stop”). For field stop IGBTs, it is important to carefully control the charge levels in the buffer layer and the collector layer.
FIG. 1 shows a conventional field-stop IGBT formed in an N− epitaxial layer having a thickness of approximately 45 micrometers and dopant concentration of approximately 2E14/cm3. A semiconductor substrate supports the epitaxial layer having backside layers including an N-buffer layer with 2.5E12/cm2 charge and a P collector layer with 1E13/cm2 charge. A drain/collector electrode is attached at the bottom surface to the P-collector layer.
In order to ensure a high breakdown voltage for a field stop IGBT, a tight control on the charge levels of the backside layers is required. It is further necessary to control the backside layer charges with a high degree of accuracy to achieve a good trade-off between the conduction loss (VCE, sat) and switching losses.
To form the backside layers, conventional methods of manufacturing implement backside processing steps as shown in FIGS. 1A-1 to 1A-5 and FIGS. 1B-1 to 1B-5. FIG. 1A-1 shows a starting material of an N type silicon layer having a dopant concentration of 2E14/cm3. The starting material is a single semiconductor substrate layer, without an additional epitaxial layer atop. In FIG. 1A-2, the top side processing steps are completed to form the IGBT structures on the top side of the substrate. In FIG. 1A-3, a backside grinding is performed to reduce the starting substrate layer to a predefined thickness. In FIG. 1A-4, a backside N-type implant is performed to first form a N buffer layer at the bottom of the N− epitaxial layer and then a P-type implant is carried out to form the bottom P collector layer. In FIG. 1A-5, a backside metal layer is formed to function as the drain/collector electrode. The processes require two backside implants and activation/anneal operations. The anneal processes on the backside layer can only be performed at a low temperature due to the limitations imposed by the already existing top metal layer—the metal layers cannot withstand a high annealing temperature. However, such limitation causes poor and irregular performance of the N-buffer layer to block the leakage current. The poor performance is caused by the fact that the N-buffer is formed as a blocking junction, and the block junction requires an anneal process to repair all crystal damages or the device will have a high leakage current.
FIGS. 1B-1 to 1B-5 illustrate an alternative conventional method for manufacturing the IGBT. In FIG. 1B-1, a starting material of silicon substrate is formed with a lower N-substrate layer having the volumetric doping concentration of the N-buffer layer supporting an N-epitaxial layer over it having a dopant concentration of 2E14/cm3. In FIG. 1B-2, the top processing steps are completed to form the IGBT structures on the top side of the substrate. In FIG. 1B-3, a backside grinding is performed to reduce the lower N substrate layer to a predefined thickness. This pre-defined thickness together with the volumetric doping concentration of the lower N substrate layer ideally result in the desired per area charge level (e.g., 2.5E12/cm2) of the N buffer region. In FIG. 1B-4, a backside P-type implant is carried out to form the bottom P type layer. In FIG. 1A-5, a backside metal layer is formed to function as the drain electrode. This method does not require a high temperature anneal after backgrinding for the N buffer layer because the N buffer layer is already doped as the starting lower substrate layer. However, the manufacturing processes encounter a difficulty being unable to accurately control the back grinding thickness within a tightly controlled tolerance. Variations in the back grinding thickness will result in varying thicknesses of the N buffer layer and thus varying charge levels in the N buffer layer. Performance of the IGBT device may be adversely affected due to the high sensitivity of such device to the N-buffer charge variations caused by thickness uncertainties of the N-buffer layer. Furthermore, the performance of device blocking/PNP gain are also very sensitive to the N-buffer charges and that again may be jeopardized by the uncertainties of thickness control in the backside grinding process.
Accordingly, there is a need to provide a new manufacturing method to resolve the above discussed difficulties and limitations. More particularly, it is further desired that the new manufacturing method can simplify the processing steps such that cost savings, production yields and device performance reliability may also be achieved in a new and improved field stop IGBT.